1. (i) Consider a catche (M1) and memory(M2) hierarchy with the following characteristics :
M1 : 16 K words, 50 ns access time
M2 : 1 M words, 400 ns access time

Assume 8 words cache blocks and a set size of 256 words with set associative mapping.

(a) Show the mapping between M2 and M1.
(b) Calculate the effective memory access time with a catche hit ratio of h = 0.95.

(ii) Answer the following questions with reference to processors and memory hierarchy:

(a) Explain the relationship between the integer unit and the floating point unit in most RISC processors with scalar or Superscalar organisation.

(b) Explain the difference between Superscalar and VLIW architectures in terms of H/W and S/W requirements.

(c) What are the design tradeoffs between a large register file and a large D-cache?

(iii) Define five important characteristics of parallel algorithms which are machine implement able.

2. (i) Explain how instruction set, compiler technology, CPU implementation and control, and catche and memory hierarchy affect the CPU performance and justify the effects in terms of program length, clock rate and effective CPI.

(ii)(a) What causes a processor pipeline to be under pipelined?

(b) What are the factors limiting the degree of super scalar design?

3. Explain the following concepts associated with cache and memory architecture:
(a) Low order memory interleaving
(b) Memory bandwidth and Fault tolerance
(c) Write through vs Write-back catches
(d) Physical address cache vs Virtual address cache
(e) Cache flushing policies

4. (i) Discuss the three mechanisms for instruction pipelining.

(ii) Draw the architecture of a vector supercomputer and describe it in brief.

5. Describe the following in context of system interconnection architecture: (i) Ring and Chordal ring
(ii) Hypercube
(iii) Multistage Networks

6. Explain the following concepts related to multivector and SIMD computers:
· S-access memory organization
· Full-scale vector supercomputers
· Vector and scalar balance point
· Mini supercomputers
· Major challenges in the development of future general purpose supercomputers