1. (i) Consider the execution of the following code segment. Use Bernstein's condition to detect the maximum parallelism embedded in this code. Justify the portion that can be executed is parallel and the remaining portion that must be executed sequentially.

S1 : A = B + C
S2 : C = D + E
S3 : F = G + E
S4 : C = A + F
S5 : M = G + G
S6 : A = L + C
S7 : A = E + A

(ii) Draw a dependence graph to show all the dependences for the above code segment.

(iii) Answer the following questions:

(a) Distinguish between single threaded and multithreaded processor architecture.

(b) What difficulties will arise when a computer is scaled to become a-massively parallel processing (MPP) system.

(c) Explain the differences between superscalar and very large instruction word (VLIW) architectures in terms of hardware and s/w requirements.

(d) Describe the advantages and short-comings of daisy-chaining scheme for bus arbitration in a multiprocessor system.

(e) Plot the graph showing the speedup factors and optimal number of pipeline stages for a linear pipeline unit. What are the pros and cons?

2 Explain the following terms:
(a) Private cache vs Shared cache
(b) Ring and chordal rings
(c) Hardwired vs Microcoded control.
(d) Network partitioning for multicasting communication.
(e) HIT ratio.

3. (i) What are the two approaches to interleaved memory organization? What is its significance? Draw a complete eight-way high order interleaving diagram. Also explain what are the major and minor cycles for pipelined access and how these two are related?

(ii) What is the architectural distinction between RISC and CISC processors? Explain the concept of overlapping register windows in the SPARC architecture diagrammatically?

4. Distinguish among the following:

(i) Data flow and reduction computers
(ii) Coarse grain and medium grain level parallelism
(iii) Numeric processing and symbolic processing computers in terms of common operations, memory requirements and processor architecture.

5. Answer the following questions as applied to multiprocessors and multicomputers: [15]

(a) Buffering flow control using virtual cut through routing
(b) Blocking flow control in wormhole routing
(c) Virtual networks and sub networks

6. Answer the following questions:

(i) What is the purpose of prefetch buffers in instruction pipelining?

(ii) What is the cache coherence problem? What are the cache inconsistencies resulting from it? Give a solution to this problem?

(iii) What are the tradeoffs in scalability analysis?