1.(a) Compare dynamic connection networks such as bus systems, multistage interconnection networks and crossbar switch networks in terms of the following characteristics:

(i) Bandwidth
(ii) Hardware complexity such as switching, arbitration, wires etc.
(iii) Network latency
(iv) Scalability

(b) Compare and also comment on the static connection networks: Linear Array, Ring, Binary tree, 2D-Mesh in terms of the following characteristic:

· Node degree
· Network diameter
· No. of Links
· Bisection width
· Symmetry

(c) A 2-Level memory system has 8 virtual pages on a disk to be mapped into 4 page frames (PF) in the main memory. A certain program generated the following page trace: 1, 0, 2, 2, 1, 7, 6, 7, 0, 1, 2, 0, 3, 0, 5, 4

(i) Show the successive virtual pages residing in the 4 page frames with respect to the above page trace using the LRU replacement policy. Compute the hit ratio in the main memory. Assume PFs are initially empty.

(ii) Repeat (i) for the circular FIFO page replacement policy. Compute the hit ratio in the main memory.

2.(a) Discuss the various parallelism levels in programs and their implementation issues from the programmer and compiler designer's viewpoint.

(b) Analyze techniques namely
(1) Grain packing and scheduling
(2) Static multiprocessor scheduling to minimize communication latency and optimize grain size with appropriate example

3.(a) Define the following with the appropriate formulae:
· Clock rate and CPI
· MIPS rate
· Throughput rate

(b) Distinguish between the following:

· Multiprocessors and multicomputers based on their structures, resource sharing and inter processor communication.

· NUMA and COMA computers

· Single- threaded and multi-threaded processor architecture.

4. (a) List five challenging parallel application areas.

(b) Summarize important characteristics of parallel algorithms which are machine implementable.

(c) Discuss in detail the trade-offs in scalability analysis.

5. Explain the following terms associated with cache design:

(a) Write- through versus Write-back caches

(b) Cacheable vs Noncacheable data

(c) Private caches vs shared caches

(d) Cache flushing policies

(e) Factor affecting cache hit ratio

6. (a) What is VLIW architecture? Explain pipelining in VLIW processors.

(b) Compare and contrast Central Arbitration with Distributed Arbitration.

(c) What is the purpose of prefetch buffers in instruction pipelining?