Note : Question one is compulsory. Answer any three from
the rest.
1. (i) Consider a catch (M1) and memory (M2) hierarchy
with the following characteristics: M1: 16 K words,
50 ns access time M2: 1 M words, 400 ns access time
Assume eight word catche blocks and a set size of 256
word with set-associative mapping
· Show the mapping between M2 and M1
·Calculate the effective memory access time with
a catch hit ratio of h = 0.95.
(ii) What causes a processor pipeline to be under pipelined?
(iii) What is meant by a hierarchical bus system for
multiprocessing system? `
2 Discuss the following the context of parallel languages
and compilers:
(i) Parallel code generation
(ii) Parallel flow control
(iii) Parallel arrays
3(i) Describe the important characteristics of parallel
algorithms which are machine implementable.
(ii) Discuss the is efficiency concept in the context
of the efficiency of a parallel algorithm.
4. Discuss the following in the context of computer
architecture:
(i) Distributed Arbitration
(ii) Snoopy bus protocol
(iii) Branch handling in instruction pipeline
5. (i) Discuss the architectural environment for a
multithreaded computer model.
(ii) What are the limitations of conventional UNIX
for parallel processing systems.
(iii) What is the sector mapping cache? Discuss with
the help of an example.
6. Explain the structural and operational difference
between register to register and memory to memory architecture
in building multipipelined supercompter for vector processing.
Comment on the advantages and disadvantages in using
SIMD computers as compared with the use of pipelined
supercomputer for vector processing.
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