m
 
   Colleges and Courses  |  College Admissions  |  Campus Life  |  Academic Projects  |  Exam Notifications  |  Jobs Abroad  |  Discussions  |  Home
  IGNOU QUESTION PAPERS:


Google
 
MCA Semester 4 CS-12
Computer Architecture - Jan 2001


Submitted by: Cle_5            1  | 2 | 3 | 4 | 5 Submit your Code

Note : Question one is compulsory. Answer any three from the rest.

1(i) The execution times (in seconds) of four programs on three computers are given below:
Execution Time (in seconds)
Program Computer A Computer B Computer C
P1 1 10 20
P2 1000 100 40
P3 500 1000 50
P4 100 500 100


Assume that 100,000,000 instructions were executed in each of the four programs. Calculate the MIPS rating of each program on each of the three machines. Based on these ratings. Can you draw a clear conclusion regarding the relative performance of the three computers?

(ii) Answer the following questions:
(a) What causes a processor pipeline to be underpipelined?
(b) What are the factors limiting the degree of superscalar design?
(c) Compare the instruction set architecture in RISC and CISC processors in terms of instruction formats and addressing modes.
(d) Factors affecting cache hit ratio.

2 Compare the relative merits of the three cache memory organizations:

(i) Fully-associative cache
(ii) Set-associative cache
(iii) Sector mapping cache

3. Answer the following questions on designing scalar RISC or Superscalar RISC processors: [15]

(i) Why do most RISC integer units use 32 general-purpose registers?

(ii) What are the design tradeoffs between a large register file and a large D-cache?

(iii) Explain the relationship between the integer unit and floating point unit in most RISC processors with scalar or superscalar organization.

4. Answer the following questions on pipelining and superscalar techniques:

(i) Speed-up factors and the optimal number of pipeline stages for a linear pipeline unit.

(ii) Mechanisms for instruction pipelining. ]

5. Explain the following as applied to multiprocessors and multicomputers:

· Buffering flow control using virtual cut through routing
· Blocking flow control in warm hole routing
· Virtual networks and sub networks

6. Distinguish among the following vector processing machines in terms of architecture and performance range:

(i) Full scale vector supercomputers
(ii) High-end mainframes or near supercomputers
(iii) Minisupercomputers or supercomputing workstations


Assignments
C Programming
SAD
C Programing
Compu Networks
Compu Architecture
Question Papers
Intro to Software
June 1995
Dec 1995
June 1995
Dec 1996
Dec 1997
Dec 1999
June 2000
Dec 2000
June 2001
Jan 2001
Dec 2002
Database Management
June 1995
Computer Architecture
June 1997
Dec 1997
June 1998
Dec 1998
June 1999
Dec 1999
June 2000
Dec 2000
Jan 2001
June 1995
Dec 2001
June 2002
Computer Architecture
June 1996
Dec 1996
June 1997
Dec 1997
June 1999
June 1998
Networking
June 1995
Dec 1999
June 2000
Dec 2000
Jan 2000
June 2001
Dec 2001
June 2002
Finance & Accounting
Dec 1996
June 1997
Dec 1997
June 1998
Dec 1998
June 1999
Dec 1999
June 2000
Dec 2000
June 2003
Numerical & Programming
June 2001
Dec 2001
Operations Research
June 1995
June 2002
June 2001
Software Engineering
Dec 2001
Dec 2002
 
TOP